The present invention relates to a technique that can be effectively adapted to semiconductor and other memory devices, and in particular relates to a technique that can be effectively utilized, for example, in a semiconductor dynamic memory device which has folded bit lines.
Japanese Patent Publication No. 39073/1980 discloses a dynamic random-access memory (hereinafter referred to as a DRAM) provided with folded bit lines.
A system has been proposed for a DRAM in which data is read from memory cells by utilizing dummy cells (or dummy memory cells) of a capacity approximately half that of the memory cells, i.e., by utilizing dummy cells (hereinafter referred to as half-size dummy cells) which have reference capacitors of a capacity about half that of capacitors used for storing data.
With a memory circuit of this type, a bit data stored in the memory cell is detected by a differential sense amplifier which compares potentials which vary according to the quantity of electric charge stored in the memory cell and the dummy cell.
According to studies conducted by the inventors, however, it has been found that it is virtually impossible to manufacture half-size dummy cells with the same process variation of that of memory cells, so that a problem concerning accuracy remains. On the other hand, it has been found that the dummy cells should be of the same size as the memory cells, i.e., each of the dummy cells (hereinafter referred to as full-size dummy cells) should be provided with a reference capacitor of a capacity substantially equal to that of the capacitor used for storing data in a memory cell. A variety of memories have been proposed employing full-size dummy cells, but these waste large quantities of power in the resetting of the dummy cells, and their sensing speed is low.
The inventors have studied these problems, and have contrived a memory device employing full-size dummy cells based upon an extremely novel idea.